A C-DAG task model for scheduling complex real-time tasks on heterogeneous platforms: preemption matters

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time application for such architectures, the designer needs to make a number of difficult choices: on which processor should a certain task be implemented? Should a component be implemented in parallel or sequentially? These choices may have a great impact on feasibility, as the difference in the processor internal architectures impact on the tasks' execution time and preemption cost. To help the designer explore the wide space of design choices and tune the scheduling parameters, in this paper we propose a novel real-time application model, called C-DAG, specifically conceived for heterogeneous platforms. A C-DAG allows to specify alternative implementations of the same component of an application for different processing engines to be selected off-line, as well as conditional branches to model if-then-else statements to be selected at run-time. We also propose a schedulability analysis for the C-DAG model and a heuristic allocation algorithm so that all deadlines are respected. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We demonstrate the effectiveness of our approach on a large set of synthetic experiments by comparing with state of the art algorithms in the literature

An analysis and Simulation Tool of Real-Time Communications in On-Chip Networks: A Comparative Study

International audienceThis paper presents Real-Time Network-on-chip-based architecture Analysis and Simulation tool (ReTiNAS), with a special focus on real-time communications. It allows fast and precise exploration of real-time design choices onto NoC architectures. ReTiNAS is an event-based simulator written in Python. It implements different real-time communication protocols and tracks the communications within the NoC at cycle level. Its modularity allows activating and deactivating different NoC components and easily extending the implemented protocols for more customized simulations and analysis. Further, we use ReTiNAS to perform a comparative study of analysis and simulation for different communication protocols using a wide set of synthetic experiments

Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes.

Cyber physical systems (CPS) and Internet of Objects (IoT) are generating an unprecedentedvolume and variety of data that needs to be collected and stored on the cloud before beingprocessed. By the time the data makes its way to the cloud for analysis, the opportunity totrigger a reply might be late.One approach to solve this problem is to analyze the most time-sensitive data at the net-work edge, close to where it is generated. Thus, only the pre-processed results are sent tothe cloud. This computation model is know as *Fog Computing* or *Edge computing*. Crit-ical CPS applications using the fog computing model may have real-time constraints becauseresults must be delivered in a pre-determined time window. Furthermore, in many relevantapplications of CPS, the processing can be parallelized by applying the same processing ondifferent sub-sets of data at the same time by the mean parallel programming techniques. Thisallow to achieve a shorter response time, and then, a larger slack time, which can be used toreduce energy consumption.In this thesis we focus on the problem of scheduling a set of parallel tasks on multicoreprocessors, with the goal of reducing the energy consumption while all deadlines are met. Wepropose several realistic task models on architectures with identical and heterogeneous cores,and we develop algorithms for allocating threads to processors, select the core frequencies, andperform schedulability analysis. The proposed task models can be realized by using OpenMP-like APIs.Les systèmes cyber-physiques (CPS) et d’Internet des objets génèrent un volume et une variété des données sans précédant. Le temps que ces données parcourent le réseau dans son chemin vers le cloud, la possibilité de réagir à un événement critique pourrait être tardive. Pour résoudre ce problème, les traitements de données nécessitant une réponse rapide sont faits à proximité d’où les données sont collectées. Ainsi, seuls les résultats du pré-traitement sont envoyées au cloud et la réaction pourrai être déclenché suffisamment rapide pour préserver l’intégrité du système. Ce modèle de calcul est connu comme Fog Computing. Un large spectre d’applications de CPS ont des contraintes temporelle et peuvent être facilement parallélisées en distribuant les calculs sur différents sous-ensembles de données en même temps. Ceci peut permettre d’obtenir un temps de réponse plus court et un temps de creux plus large. Ainsi, on peut réduire la fréquence du processeur et/ou éteindre des parties du processeur afin de réduire la consommation d’énergie. Dans cette thèse, nous nous concentrons sur le problème d'ordonnancement d’un ensemble de taches temps-réels parallèles sur des architectures multi-coeurs dans l’objectif de réduire la consommation d’énergie en respectant toutes les contraintes temporelles. Nous proposons ainsi plusieurs modèles de tâches et des testes d'ordonnançabilité pour résoudre le problème d’allocation des threads aux processeurs. Nous proposons aussi des méthodes qui permettent de sélectionner les fréquences et les états des processeurs. Les modèles proposés peuvent être implantés comme des directives dans la même logique que OpenMP

Migrate when necessary: toward partitioned reclaiming for soft real-time tasks

International audienceThis paper presents a new strategy for scheduling soft real-time tasks on multiple identical cores. The proposed approach is based on partitioned CPU reservations and it uses a reclaiming mechanism to reduce the number of missed deadlines. We introduce the possibility for a task to temporarily migrate to another, less charged, CPU when it has exhausted the reserved bandwidth on its allocated CPU. In addition, we propose a simple load balancing method to decrease the number of deadlines missed by the tasks. The proposed algorithm has been evaluated through simulations, showing its effectiveness (compared to other multi-core reclaiming approaches) and comparing the performance of different partitioning heuristics (Best Fit, Worst Fit and First Fit)

The HPC-DAG Task Model for Heterogeneous Real-Time Systems

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Building Time-Triggered Schedules for Typed-DAG Tasks with Alternative Implementations

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PRUDA: An API for Time and Space Predictible Programming in NVDIA GPUs using CUDA

International audienceRecent computing platforms combine CPUs with different types of accelerators such as Graphical Processing Units (GPUs) to cope with the increasing computation power needed by complex real-time applications. NVIDIA GPUs are compound of hundreds of computing elements called CUDA cores, to achieve fast computations for parallel applications. However, GPUs are not designed to support real-time execution , as their main goal is to achieve maximum through-put for their resources. Supporting real-time execution on NVIDIA GPUs involves not only achieving timely predictable calculations but also to optimize the CUDA cores usage. In this work, we present the design and the implementation of PRUDA (Predictable Real-time CUDA), a programming platform to manage the GPU resources, therefore decide when and where a real-time task is executed. PRUDA is written in C and provides different mechanisms to manage the task priorities and allocation on the GPU. It provides tools to help a designer to properly implement real-time schedulers on the top of CUDA

Preemption-Aware Allocation and Deadline Assignment for Conditional DAGs on Partitioned EDF

International audienceComplex heterogeneous hardware platforms are increasingly used for implementing critical real-time applications like ADAS and autonomous driving. To better support real-time workloads, GPUs have evolved to allow preemption for computationally intensive tasks and for graphical tasks. However in some cases the cost of preemption can be very high, and must be accounted for in the design and in the scheduling analysis.In this paper, we address the problem of allocating a set of real-time tasks, modeled by conditional directed acyclic graphs, onto multiprocessor platforms under partitioned preemptive Earliest Deadline First scheduling, assuming a non-negligible cost of preemption. We propose methods for assigning intermediate deadlines and offsets to real-time C-DAGs, so to remove unnecessary preemptions and reduce the total preemption overhead. The effectiveness of the proposed techniques is evaluated using a large set of synthetic tasks sets

Toward Precise Real-Time Scheduling on NVidia GPUs

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Contention-free scheduling of PREM tasks on partitioned multicore platforms

International audienceCommercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the delays due tomemory contention. However, without proper support from the hardware (e.g. a real-time bus scheduler), it is difficult to estimate such upper bounds.This work aims at avoiding contention for a set of tasks modeled using the Predictable Execution Model (PREM), i.e. each task execution is divided into a memory phase and a computation phase, on a hardware multicore architecture where each core has its private scratchpad memory and all cores share the main memory. We consider non-preemptive scheduling for memory phases, whereas computation phases are scheduled using partitioned preemptive EDF. In this work, we propose three novel approaches to avoid contention in memory phases: (i) a task-level time-triggered approach, (ii) job-level time-triggered approach, and (iii) on-line scheduling approach. We compare the proposed approaches against the state of the art using a set of synthetic experiments in terms of schedulability and analysis time. Furthermore, we implemented the different approaches on an Infineon AURIX TC397 multicore microcontroller and validated the proposed approaches using a set of tasks extracted from well-known benchmarks from the literature